1. Field of the Invention
The present invention relates to a method of manufacturing a stack-type semiconductor device in which a plurality of semiconductor elements are stacked, and to a method of manufacturing a stack-type electronic component in which a plurality of electronic components are stacked.
2. Description of the Related Art
In order to realize downsizing, higher-density packaging, and the like of a semiconductor device, a stack-type multichip package in which a plurality of semiconductor elements are stacked and sealed in one package has been in practical use in recent years. In the stack-type multichip package, the plural semiconductor elements are stacked in sequence on a circuit board via an adhesive film. Electrode pads of the semiconductor elements are electrically connected to electrode parts of the circuit board via bonding wires. Such a stacked structure is packaged by sealing resin, whereby the stack-type multichip package is formed.
In the stack-type multichip package, the upper semiconductor element, if smaller than the lower semiconductor element, does not interfere with the bonding wires of the lower semiconductor element. However, such a structure greatly limits applicable semiconductor elements. Therefore, an effort is being made to widen the applicable range to semiconductor elements in the same shape and to semiconductor elements with an upper one being larger than a lower one. Stacking semiconductor elements in the same shape or stacking a larger semiconductor element on an upper side of a lower semiconductor involves a possibility that bonding wires of the lower semiconductor element come in contact with the upper semiconductor element. Therefore, it is important to prevent the occurrence of insulation failure, short circuit, and the like ascribable to the contact of the bonding wires.
So, there is an art to make an adhesive layer for bonding semiconductor elements thick enough to prevent bonding wires of a lower semiconductor element from coming in contact with an upper semiconductor element (see, for example, Japanese Patent Laid-open Application No. 2001-308262, Japanese Patent Laid-open Application No. 2004-072009). Specifically, an adhesive layer having a thickness large enough to prevent the contact of the bonding wires is formed on a rear surface side of the upper semiconductor element. To form the adhesive layer, for example, an adhesive film and a dicing film are affixed in sequence on a rear surface of a semiconductor wafer and the semiconductor wafer is divided. After the semiconductor elements are stacked via the adhesive layer and the bonding wires are taken into the adhesive layer whose viscosity has become low by heating, the adhesive layer is cured, whereby the semiconductor elements are bonded together.
Another proposed art is to form an insulating layer on a rear surface side of an upper semiconductor element, thereby preventing insulation failure, short circuit, and the like ascribable to the contact of bonding wires of a lower semiconductor element with the upper semiconductor element (see, for example, U.S. Pat. No. 6,657,290). For example, an insulator film (insulating layer) and an adhesive film (adhesive layer) are affixed on a rear surface of a semiconductor wafer in sequence. The semiconductor wafer is divided together with the films, whereby semiconductor elements are made. Such a semiconductor element is bonded on the lower semiconductor element. Insulation failure and short circuit ascribable to the contact of the bonding wires are prevented by the insulating layer which is stacked together with the adhesive layer on the rear surface of the upper semiconductor element.
As described above, for preventing connection failure of the bonding wires based on the thickness of the adhesive layer interposed between the semiconductor elements, the adhesive layer needs to be sufficiently thick. In addition, since the bonding wires connected to the lower semiconductor element are partly taken into the adhesive layer, the adhesive layer needs to have viscosity not causing the deformation or connection failure of the bonding wires. It has been found out that the use of a low-viscosity, thick adhesive layer (adhesive film) causes various problems if conventional manufacturing processes, materials, and the like are simply applied.
A complex film formed by stacking a low-viscosity, thick adhesive film on a conventional dicing film is low in removability from a release tape, and failure in bonding it to a semiconductor wafer is liable to occur. Further, simply increasing removability of the complex film from the release tape may possibly cause inconvenience in picking up the semiconductor element from the dicing film. That is, pickup failure of the semiconductor element is liable to occur.
Further, if viscosity of the adhesive layer at the bonding time is made too low in order to prevent the deformation and connection failure of the bonding wires that might occur when the elements are bonded, an adhesive sticks out from an end face of the element or a layered form cannot be maintained. Consequently, the lower bonding wires easily come into contact with the upper semiconductor element. On the other hand, if the viscosity of the adhesive layer is too high at the bonding time, the bonding wires are liable to suffer deformation and connection failure, and in addition, portions left unfilled with adhesive resin is liable to occur under the bonding wires.
In a subsequent resin molding process, it is also difficult to fill the resin in the resin unfilled portions under the wires, and therefore, bubbles due to the resin unfilled portions remain. The occurrence of bubbles in the semiconductor device tends to cause peeling starting from the bubbles and leakage in a reliability test on hygroscopic properties, solder reflow, and the like. This will be a cause of lowering reliability of the semiconductor device. These problems are likely to occur not only in a semiconductor device in which a plurality of semiconductor elements are stacked but also in a stack-type electronic component in which various electronic components are stacked and packaged.